With the recent revolutionary progress in the LSI (Large Scale Integration) technology, a variety of information processing equipment and information communication equipment have been developed and marketed. With these equipment, a CPU (Central Processing Unit) or other processors execute a preset program code to render variegated processing services.
On the other hand, reduction in power consumption in information equipment is becoming incumbent because this is relevant to the elongation of the useful life of a battery in battery driven type information equipment. Even in information equipment that can be driven apparently limitlessly with the commercial power source, power saving is recommended from the socio-ecological aspect that supply of natural resources cannot be limitless.
Within the information equipment, the proportion of power consumption of a processor as its main controller in the power consumption of the entire equipment is rather high. Stated differently, power saving of the processor leads to realization of power saving of the entire information equipment. By and large, the operating speed of the processor becomes higher the higher becomes the operating frequency, with the power consumption then tending to be increased.
For example, the Japanese Laying-Open Patent Publication H-11-194849 discloses a data processing method and apparatus in which a preset processing operation can be finished within a preset processing time without uselessly increasing the power consumption and in which the setting operation may be facilitated even if the task processing capacity is changed.
In the data processing apparatus disclosed in the above cited publication, the processing capacity and the processing time in case a micro-computer executes variegated processing operations are registered in capacity registration means and in the time storage means, respectively, the processing capacity and time are computed for variegated processing operations carried out by the micro-computer, and the processing capacity is divided by the processing time to calculate the processing speed of the micro-computer to change the frequency of reference clocks. Since the processing speed of the micro-computer is varied with the processing capacity and the processing time, a preset processing operation can be positively finished within a preset processing time, while the frequency of the reference clocks can be set at an optimum value, thus preventing the power consumption in the data processing apparatus from increasing wastefully.
However, with the data processing method and apparatus disclosed in the above cited publication, it is envisaged to reduce the power consumption by solely changing the operating clock frequency of the processor. Stated differently, while the power consumption per unit time is decreased by diminishing the operating clock frequency, the required time for completing each processing is elongated, so that no sufficient effect in reducing total power consumption may be achieved. Specifically, the extent of saving in power consumption achieved is not higher than the amount of power consumption when the processor is in the idling state, with the result that power consumption cannot be saved effectively.
Moreover, with the data processing method and apparatus, disclosed in the above cited publication, it is presupposed that the processing timing of each processing is pre-set, and that, by sequentially performing respective processing operations without interruptions, the totality of the processing operations can be finished in time. Thus, the data processing method or apparatus cannot be applied to a system in which it may become necessary to interrupt a given processing operation to proceed to a more urgent processing, such as real-time processing.
The Japanese Laying-Open Patent Publication 2000-122747 discloses a controlling method and apparatus in which a clock generator supplying clocks to a digital signal operating processor is provided and in which the frequency of the clocks supplied from the clock generator to a digital signal operating processor is controlled on the basis of the operating processing quantity in the digital signal operating processor to diminish the power consumption.
Moreover, with the data processing method and apparatus disclosed in the above cited publication, it is contemplated to reduce the power consumption by solely changing the operating clock frequency of the processor. In other words, while the power consumption per unit time may be decreased by diminishing the operating clock frequency, the required time for completing each processing is elongated, with the result that the effect in reducing total power consumption is not that high. Specifically, the extent of saving in power consumption achieved is not higher than the amount of power consumption when the processor is in the idling state, so that no sufficient effect in the saving in power consumption may be achieved.
Additionally, with the controlling method and apparatus, disclosed in the above cited publication, the operating frequency is computed from the proportion of the idling time. However, under a multi-tasking environment designed for carrying out a large number of tasks operating with different periods, it is not possible to compute the proportion of the idling time.
On the other hand, in the SS and SD scheduling techniques, as proposed in a treatise by Takanori Okuma, Tohru Ishihara and Hiroto Yasuura, entitled ‘Real-Time Task Scheduling for a Variable Voltage Processor’ (IEEE 12th International Symposium on System Synthesis, November 1999), it is presupposed that the start time of task execution is known prior to system running. This indicates that rescheduling is necessary to perform every time a task is supplemented or deleted. Moreover, this scheduling must be performed by computing the scheduling with the least common multiple of the periods of the respective periodic tasks as a period. With the least common multiple of these periods being not sufficiently small, the task supplementing or deleting efficiency is worsened.
Additionally, with the DD scheduling technique, proposed in this treatise, the scheduling which takes into account the fact that a task is started with a specified pattern is not used, as in periodic sled, so that no sufficient effect in reducing power consumption may be achieved.
The technique termed “Task Based Static Scheduling” as proposed in a treatise by Yann-Hang Lee and C. M. Krishna, entitled “Voltage-Clock Scaling for Low Energy Consumption in Real-time Embedded Systems” (IEEE Sixth International Conference on Real-Time Computing Systems and Applications, December 1999), is premised on scheduling a task by a static priority method. However, the static priority method is known to be inferior to the fastest deadline priority scheduling, in its scheduling capability, such that this technique also is not satisfactory in its effect in diminishing the power consumption.
By and large, if the operating frequency is increased, a processor tends to become faster in its operating speed, but is increased in power consumption, as discussed above. On the other hand, the power source voltage, in other words, the power consumption, must be increased with the processor's operating frequency. However, as the design rule in the LSI manufacturing process becomes finer, an upper limit is set on the power source voltage, so that, in reality, it has not been practiced to raise the frequency by raising the voltage.
In a system in which the processor's operating frequency as well as the power source voltage can be changed through dynamic control, it may be thought to be feasible to adaptively change the operating frequency necessary for processing respective booted tasks without delay and to decrease the processor's power consumption by determining the optimum power source voltage responsive to the operating frequency changing with lapse of time. However, there lacks the prior art technique which has brought this to realization.